For many applications, such as system-on-chip (SOC) architecture, it is desirable to integrate logic devices and interface circuits based upon metal-oxide-semiconductor (MOS) field-effect transistors and non-volatile memory (NVM) devices on a single chip or substrate. MOS transistors are typically fabricated using a standard or baseline complimentary-metal-oxide-semiconductor (CMOS) process flows. NVM devices can include silicon-oxide-nitride-oxide-semiconductor (SONOS) based transistors, including charge-trapping gate stacks in which a stored or trapped charge changes a threshold voltage of the non-volatile memory transistor to store information as a logic 1 or 0. The integration of these dissimilar transistors in SOC architecture is challenging and becomes even more problematic as the transistors are scaled to smaller geometries.